1. Field of Art
The disclosure generally relates to the field of static timing analysis and more specifically to prioritizing timing violations identified by static timing analysis.
2. Description of the Related Art
Integrated circuit designs are simulated to assess their performance and determine whether the design works as expected. For instance a circuit design may be simulated to determine the behavior of the circuit design in response to certain input signals. Circuit designs may also be analyzed to determine whether the different stages of the circuit meet the timing requirements. For instance, a circuit design is analyzed to determine whether the propagation delay of a timing path is within the setup time and the hold time of a flip-flop connected to the end of the timing path.
At the end of the analysis of the circuit design, the analysis tools may identify multiple timing violations. The designer of the circuit reviews the results of the analysis and fixes the timing violations identified by the analysis tool. As the size and complexity of the integrated circuit increases, the number of timing violations that may be found by the analysis tool and the complexity of fixing the timing violations also increases. The process of analyzing these violations, prioritizing them, and identifying steps to fix these violations often involve manual steps. As a result, conventional techniques for processing these timing violations are often time consuming and significantly slow down the overall design process for a complex circuit.